1. Field of the Invention
The invention relates to an inverter, and more particular to an inverter structure disposed in a SRAM.
2. Description of the Prior Art
An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer system as a cache memory.
Please refer to FIG. 1, which shows a circuit diagram of typical six-transistors SRAM (6T-SRAM) 10. The 6T-SRAM cell 10 comprises pull-up transistors 12 and 14, pull-down transistors 16 and 18, and access transistors 20 and 22. These six transistors constitute a set of flip-flops. Pull-up transistors 12, 14 and pull-down transistors 16, 18 constitute a latch that stores data in the storage node 24, 26. Because the pull-up transistors 12, 14 act as power load devices they can be replaced by resistors. At this point, the static random access memory is a four-transistors SRAM (4T-SRAM).
Generally speaking, the pull-up transistors 12, 14 of the 6T-SRAM cell 10 comprise p-type metal oxide semiconductor (PMOS) transistors. The pull-down transistors 16, 18 and the access transistors 20, 22 comprise n-type metal oxide semiconductor (NMOS) transistor. The pull-up transistor 12 and the pull-down transistor 16 constitute an inverter, and a series circuit 28. One end of the series circuit 28 is connected to a power supply 32 and the other end of the series circuit 28 is connected to a ground 34. Equally, the pull-up transistor 14 and the pull-down transistor 18 constitute another inverter and a series circuit 30. One end of the series circuit 30 is connected to the power supply 32 and the other end of the series circuit 30 is connected to the ground 34.
Additionally, the storage node 24 is connected to the respective gates of the pull-down transistor 18 and the pull-up transistor 14. The storage node 24 is also connected to the drains of the pull-down transistor 16, pull-up transistor 12 and the access transistor 20. Equally, the storage node 26 is connected to the respective gates of the pull-down transistor 16 and the pull-up transistor 12. The storage node 26 is also connected to the drains of the pull-down transistor 18, pull-up transistor 14 and the access transistor 22. The gates of the access transistors 20 and 22 are respectively coupled to a word line 36, and the sources are coupled to a relative data line 38.
The aggressive scaling of MOS transistors faces severe challenges to the effective capacitance, which is usually expressed as dielectric inversion thickness (Tox_INV). When a gate dielectric layer is in an inversion condition, the gate possesses less carrier mobility than metal materials, thus causing lower effective capacitance. There are two primary methods for improving the effective capacitance. One is to improve the property of the gate dielectric layer, such as using high-K materials or decreasing the thickness of the gate dielectric layer. The other one is to decrease the depletion region of the gate, such as doping atoms or implanting ions on the polysilicon gate to improve the carrier mobility.
A common technique used in industry today for effectively decreasing the Tox_INV involves conducting p-type and n-type polysilicon doping process after a gate conductive layer is deposited in the p-type and n-type transistor region. As the inverter structure disclosed in the aforementioned 6T-SRAM typically includes a polysilicon gate shared between the PMOS transistor and the NMOS transistor, problem such as dopant diffusion often arise and increases the random single bit (RSB) failure rate in the memory array.
It would thus be highly desirable to provide a method for fabricating an embedded SRAM with improved RSB failure rate.